Partially-ordered cams used in ternary hierarchical address searching/sorting

ABSTRACT

An apparatus and method that utilizes partial ordering of ternary hierarchical addresses and their associated masks entries in both binary and ternary content addressable memories (CAMs) for providing fast searches and while reducing address table size used in the processing of communication system (e.g., Internet Protocol (IP), layer-3 switches and ATM switches using E.164 addressing) addresses for identifying the source and destination of each digital packet data.

FIELD OF THE INVENTION

[0001] The invention relates to digital hierarchical address filteringand more specifically to methods for increasing the rate at whichhierarchical address filtering, such as the network address contained ina packet, can be performed.

BACKGROUND OF THE INVENTION

[0002] Address translation is the process of mapping an address, such asthe network address contained in a packet, to some desired information.Examples of desired information include determining the output port of aswitch to which a packet should be sent, or determining the address ofthe next-hop router for the routing of IP (Internet Protocol) datagrams.Address filtering is similar to address translation, except that insteadof finding the data associated with some address, it is only importantto determine whether a given address exists in a table of addresses.Throughout this disclosure, the phrase “address translation” encompassesboth address translation and address filtering.

[0003] Addresses can be placed into two categories with regard toprocessing: flat and hierarchical. Flat addresses are those addressesthat have no internal structure that is useful from a processing aspect.Ethernet addresses are an example of a flat address. Although Ethernetaddresses have some structure to them (e.g., one part of the Ethernetaddress denotes the manufacturer of the equipment using the givenEthernet address), the structure is not relevant to protocol processingoperations, such as routing. Many techniques have been developed foraccelerating flat address translation.

[0004] Hierarchical addresses are those addresses that have an internalstructure that is useful for protocol processing. Examples ofhierarchical addresses include IPv4 addresses, IPv6 addresses, E.164addresses (used in ATM-asynchronous transfer mode), and telephonenumbers. To better illustrate the internal structure of a hierarchicaladdress, a telephone number is used. Consider a telephone number: (908)979-1010. The highest level of the hierarchy is denoted by the “areacode” 908. The next level of the hierarchy is the “central office code”979. The lowest level of the hierarchy is the “station number” 1010. Thehierarchical structure of the telephone number is used to determine howto route a call through the telephone network. For example, if a callboth originates and terminates in the 979 central office, then the phonecall passes only through the 979 central office. If a call bothoriginates and terminates in the 908 area, then no long-distance carrieris used to carry the call. Note that a flat address is a hierarchicaladdress with a single level of hierarchy. Thus, any address translationtechniques that operate on hierarchical address can be applied to flataddresses as well.

[0005] The main importance of the structure of hierarchical addresses isthat there is no need to store information about every single address inorder to be able to process all addresses. Information about entireclasses of addresses can be stored in a single entry. For example, for acall that originates from area code 908 and terminates in some otherarea code, the correct action is to forward the call to a long distancecarrier, regardless of the specific terminating area code.

[0006] The tables used for hierarchical address translation can bethought of as a sieve. Consider the following example, as shown in FIG.1, of a translation table that might exist in the 979 central officeswitch (X's represent “wildcard” or “don't care” values that match alldigits). Telephone numbers are compared with table entries in order fromtop to bottom looking for a matching entry. The telephone number 908 9791035 would match entry A in the table, and the call would be routed tothe station number 1035. The telephone number 201 829 5136 matches entryD of the table and would be routed to a long distance carrier fortransport. Note that any telephone number that matches an entry also maymatch some of the entries that follow. The fact that entries areexamined in order assures that routine is done correctly.

[0007] Other methods can be used to search the table that will providethe same result as if the table were searched serially. One technique isto use a tree structure, such as a PATRICIA (Practical Algorithm ToRetrieve Information Coded In Alphanumeric) tree. The Art of ComputerProgramming (Knuth); Introduction to Algorithms (Cormen, Leiserson, andRivest). The search begins at the root of the tree, which corresponds tothe top of the hierarchy. FIG. 2 depicts such a search method andcomprises the table of FIG. 1 rearranged as shown in FIG. 2. The firstcomparison would be against just the area code 908. If 908 were found,then the entries indented under 908 would be searched. Otherwise, thecall will match the last line and be routed to a long distancePoint-of-Presence.

[0008] Another alternative would be to search all entries in parallel.As shown in FIG. 3, the table can be augmented with explicithierarchical levels assigned to each table entry. The telephone number908 979 1035 matches table entries A, C and D. The desired match isentry A, which has the highest level number (3 in this case, i.e., onlytwo entries need to be delineated A & B. The word “address” as usedabove may actually be a combination of data fields from a packet headerthat is treated as a single address for purposes of address translation.For example, the address may be a combination of source address,destination address and priority fields. It should be noted that anycombination of different header elements forms a single hierarchicaladdress, in which the different elements form part of the structure ofthe hierarchical address.

[0009] However, these approaches are limited by the constraints ofsoftware processing speeds and comparisons with table entries aretypically performed in sequential order. Thus, as network communicationspeeds increase, it becomes necessary to find high-speed translationtechniques to operate at wirespeed.

[0010] One way to achieve wirespeed is to utilize a content-addressablememory (CAM). CAMs differ from conventional RAM (random access memory),SRAM (static RAM) and DRAM (dynamic RAM) in that they are organizeddifferently. In a CAM, data is stored in locations in an arbitraryfashion. The locations can be selected by an address bus, or the datacan be written directly into the first empty location because everylocation has a special status bit that keeps track of whether thelocation has valid information in it or is empty and available foroverwriting. Once information is stored in a memory location, it isfound by comparing every bit in memory with data placed in a specialComparand register. CAMs also comprise a mask register which allowsselection of which bits will participate in the comparison. If there isa match for every bit in a location with every corresponding bit in theComparand register, a Match Flag is asserted to the user know that thedata in the Comparand register was found in memory. A priority encodersorts out which matching location has the top priority, if there is morethan one, and makes the address of the matching location available tothe user. Thus, a CAM is a memory device that allows retrieval ofinformation by specifying part of the stored information, rather than byspecifying a storage address. For example, using masking, if the entrieshex “abcd,” “abde” and “accd” were stored in a CAM, the CAM could beinstructed to return the complete contents of the entries of alllocations beginning “ab.” In this example, the CAM would return entries“abcd” and “abde.”

[0011] CAMs are generally classified as either binary or ternary CAMs.Binary CAMs store binary entries, while ternary CAMs store ternaryentries (see PCT Application No. PCT/US97/13216, WO98/07160). Binaryentries are entries that contain only 0 or 1 values, while ternaryentries are entries that contain 0, 1, or X (i.e., “don't care”) values.Note that a single ternary entry can be expressed as two or more binaryentries. In other words, a single ternary entry “1X0” can be representedby two binary entries “110” or “100”, or a single ternary entry “1XX”can be represented by four binary entries “100”, “101”, “110” or “111”,etc. Since hierarchical addresses often comprise ternary values (e.g., atelephone lookup table number “908-979-XXXX”), ternary CAMs require asmaller number of table entries to represent each hierarchical addressthan binary CAMs. However, ternary CAMs require more complex hardwareand are generally more expensive than binary CAMs. (see U.S. Pat. No.5,319,590 (Montoye)). In particular, one method to construct a ternaryCAM is to design the CAM cells and sense amps to enable the storage ofthree distinct voltage levels (high, medium and low) which wouldcorrespond to the ternary values.

[0012] The following provides a summary of existing searching methodsusing CAMs.

[0013] Expanding Each Ternary Entry into Multiple Binary Entries

[0014] While hierarchical addresses can be directly stored in ternaryCAMs, in order to be stored in binary CAMs they must first be translatedinto binary format. As discussed above, a ternary address can betranslated into two or more binary addresses. However, the number ofbinary addresses needed to represent a ternary address is 2^(m), where mis the number of bits required to represent each “don't care” value (X)in the ternary address. For example, the ternary addressABCD_(—)123X_(hex), where “X” indicates the “don't care” value, coversthe set of binary addresses given by{ABCD_(—)1230_(hex);ABCD_(—)1231_(hex); ABCD_(—)123F_(hex)} where m=4 tocover the range 0 to F. Hence, the ternary address ABCD_(—)123X_(hex)requires 16 (i.e., 2⁴) entries in the binary CAM. To that end, inaccordance with application Ser. No. 08/818,073, filed on Mar. 14, 1997,entitled “Accelerated Hierarchical Address Filtering and Translation,”(now U.S. Pat. No. 5,920,886), which is assigned to the same assignee asthe present invention, namely, Music Semiconductors, Inc., and all ofwhose disclosure is incorporated by reference herein, there is discloseda method for storing such entries in a binary CAM acting as a ternaryCAM but not having to store these entries in sequential order.

[0015] Hierarchical Level Field Searches

[0016] Another search technique involves-the use of entries in a ternaryCAM with a hierarchical level field, using a linear search of this levelfield. Fast Routing Table Lookup Using CAMs, (McAuley and Francis,1993). In particular, this technique uses a ternary CAM to store ternaryaddresses and wherein each ternary address comprises an associated levelfield. The entries may be stored in the CAM in any order. The followingis an example of how an address and mask are stored. The ternaryaddress, ABCD_(—)123X_(hex)/28 (where “28” indicates the number ofcontiguous ones in the mask), would be stored in the CAM as:

[0017] ternary field=ABCD_(—)123X_(hex)

[0018] priority field=11100_(binary) (where 11100_(binary)=28_(decimal))

[0019] The technique then begins searching from the lowest prioritylevel (i.e., the level with the longest network mask, viz.,11111_(binary)) and working towards the higher levels, depending uponwhether there are any matches. The search is altered based on the levelfield. The hierarchical address is not masked during the search and onlyparts of the level field are masked. If a match is found, the search iscomplete; if there are no matches, the level field is decremented andthe search continues. The worst case number of searches is the number ofdistinct hierarchical levels, N.

[0020] Entries in Ternary CAMs with Hierarchical Level Field. BinarySearch of Level Field

[0021] Another technique, that is an improvement of the HierarchicalLevel Field Searches, (described above), is disclosed in applicationSer. No. 08/818,073, filed on Mar. 14, 1997, entitled “AcceleratedHierarchical Address Filtering and Translation”, (now U.S. Pat. No.5,920,886), which is also assigned to the same assignee as the presentinvention, namely, Music Semiconductors, Inc., and all of whosedisclosure is incorporated by reference herein. In this technique,instead of starting at the lowest level of the hierarchy (comprising Nhierarchical levels) and working up (i.e., Hierarchical Level FieldSearches), this search technique starts in the middle and eliminatesfrom consideration one half of the remaining hierarchical levels duringeach iteration. In particular, the search starts in the middle mask(i.e., MM=N/2) and, as an example, N=32. Depending upon the searchresult, the search either moves up or down MM/2 mask levels and triesagain. The search begins looking for matches with the level field 1XXX,which will match against priority levels 16-31 since:

[0022] 16_(decimal)=10000

[0023] 17_(decimal)=10001

[0024] 24_(decimal)=11000

[0025] 31_(decimal)=11111

[0026] If there are multiple matches in this range (16-31), the mask ischanged to 11XXX (i.e., replace the most significant X of the prioritymask with a “1”). By doing so, the search range is halved, resulting ina new smaller range, viz., 24-31. After searching with the new mask, ifthere is one match, the search is complete; if there is no match, theleast significant 1 of the priority mask is replaced with a 0 (i.e., thenew mask is now 10XXX) so that the range of 16-23 is now searched.

[0027] If, on the other hand, there are no matches in this range (16-31)when the original mask 1XXX was used, the mask is changed to 0XXX whichmeans that the search is now looking at the range 0-15 of the prioritymasks, since:

[0028] 0_(decimal)=00000

[0029] 1_(decimal)=00001

[0030] 8_(decimal)=01000

[0031] . . .

[0032] 15_(decimal)=01111

[0033] After searching with the new mask, if there is one match, thesearch is complete; otherwise, the search process is repeated byreplacing the most significant X with a 1 (i.e., 01XX, searching therange 8-15). If there is no match, the least significant 1 is replacedwith a 0 (i.e., 00XX, searching The range 0-14) and the process repeateduntil a match is found.

[0034] This technique is depicted in FIG. 4 and can be summarized asfollows: The ternary CAM is first searched for an address and a priorityfield having a 1 in the most significant bit position and an X in allother bit positions, in stage 2. Stage 4 then determines if there areany matching entries, in which case, the operation proceeds to stage 8;otherwise, the least significant bit in the priority field having avalue of 1 is replaced by a value of 0 in stage 6. Stage 8 thendetermines whether any bits of the priority field have a value of X, inwhich case, the most significant bit in the priority field having avalue of X is replaced by a value of 1 in stage 10. The CAM is thensearched for the address and the modified priority field, in stage 12.Stage 14 determines whether there is a single matching entry, in whichcase, the matching entry is retrieved from the CAM in stage 16;otherwise, stages 4-14 are repeated until the test of stage 14 issatisfied and the operation terminates. Thus, one X is resolved (i.e.,replaced by a 1 or a 0) after each search until a matching entry isfound.

[0035] This technique requires, in the worst case, a number of searchesequal to the number of bits used to represent the priority field (i.e.,if N is the number of hierarchical levels represented by the priorityfield, log₂N searches are required to find a matching entry at thelowest hierarchical level, as all bits of the priority mask must beresolved).

[0036] Full-Sorted Order with Different Masks

[0037] Another technique disclosed in Fast Routing Table Lookup UsingCAMs, (McAuley and Francis, 1993) comprises the storage of entries infull-sorted order in a binary CAM with linear searching of the hierarchyusing different mask registers. Binary entries are stored in a binaryCAM and the CAM entries must be ordered inversely by level of hierarchy.Instead of using priority masks, this technique masks off the addressbeing searched in a manner similar to how the priority masks aredecremented, as described above under “Hierarchical Level FieldSearches”. In particular, this technique (shown in FIG. 5) starts withthe most precise mask of all “care” bits in the mask register andsearches the CAM through the mask register. For example, for a 32-bitaddress search, the technique would begin with all “0's” in the maskregister (a /32 mask), where “0”s correspond to “care” and “1”scorrespond to “don't cares” in a CAM search through a mask. If there isa match, the search is completed and the top CAM match (i.e., the lowestCAM address) is selected. If there is no match, the technique moves downto the next highest mask value, which is /31 in this case. The search isrepeated again through the mask register, repeating the process until asingle match is received. The worst case number of searches is Nsearches, where N is the number of hierarchical levels.

[0038] Entries in Full-Sorted Order in Binary CAM with Binary Search ofHierarchy Using Different Mask Registers

[0039] This technique, as disclosed in application Ser. No. 08/818,073,filed on Mar. 14, 1998, entitled “Accelerated Hierarchical AddressFiltering and Translation”, (now U.S. Pat. No. 5,920,886), is animprovement to Full-Sorted Order with Different Masks (discussed above)by providing a search to log₂N. This technique also starts with themedian, or half-way mask, which would be the /16 mask in a 32 mask leveladdress scheme. If there is a single match, the search is complete. Ifthere are multiple matches, the search moves to the mask half-way up,which is the /24 mask in this iteration and the search continues. Ifthere are still no matches, the search moves the other way and half-waydown, i.e., to the /8 mask in this iteration and the search continues.This process is repeated until one match is found or until no matchesare found, in which case the highest priority match from the lastmultiple match search is selected.

[0040] Full-Sorted Order

[0041] This technique is disclosed by Fast Routing Table Lookup UsingCAMs, (McAuley and Francis, 1993) and is shown in FIG. 6. In thistechnique, ternary entries are stored in sorted, i.e., inversehierarchical, order. A search takes a single cycle because the searchobtains the longest match address which is stored at the lowest CAMaddress. The major advantage of this approach is the ideal one searchcycle address resolution time. On the other hand, the downside of thistechnique is the required resorting which makes this techniqueimpractical.

[0042] IP Classless Inter Domain Routing (CIDR)

[0043] The present invention can be implemented in any type ofcommunication system where hierarchical addressing and associatedaddress masks are used. As an example, as will be disclosed below, thepresent invention can operate on the IP Classless Inter Domain Routing(CIDR) to find the “longest match” in an IP routing table. CIDR is acommon method of reducing address table size, which categorizes addressaggregations on arbitrary mask bit boundaries. CIDR reduces the size ofIP tables by making it possible to group thousands of entries under oneentry in the CIDR table. FIG. 7 shows two examples of how the 32-bitnetwork mask values are structured according to Internet Request ForComments 940 and 1519. The masks always have a structure consisting ofcontiguous “0”s on the right. A mask never has “1”s and “0”sinterleaved, or “0”s on the left and “1”s on the right. FIG. 8 showsexamples of invalid mask structures.

[0044]FIG. 9 shows four entries from a CIDR routing table (inhexadecimal format) and the network masks that relate to them. It can beseen that the mask boundaries are clearly demarcated. The number afterthe backslash indicates the number of continuous ones in the mask. Forexample, the first entry's mask is FF.FF.FF.FF, which corresponds to 32bits set to 1. This mask is an IP mask, where a 1 indicates a “care”location and a 0 indicates a “don't care.” A “care” bit means that thecorresponding bit locations of the numbers being compared must beidentical. A “don't care” bit indicates that the bit locations are notused in the comparison. The more the number of 1-bits or “cares” in amask, the less the number of possible matches. Therefore, a higher masknumber is more precise than a lower mask number. Note, an IP addresssearch may match multiple CIDR routing table entries because masking isused to further specify smaller address ranges.

[0045] In FIG. 9, the last address/mask entry actually corresponds to1100 0000 0001 1000 XXXX XXXX XXXX XXXX where the X's stand for “don'tcares.” Any search value whose top 16 bits equal 1100 0000 0001 1000would match the last entry. Note that in FIG. 9, the entries are orderedby mask value from most 1s (FF.FF.FF.FF) to the entry with the leastnumber of 1s (FF.FF.00.00, in this case). A search for CO.18.0C.15 wouldyield matches on all the entries but the first entry is chosen becauseit is the match with the longest group of 1s in the mask (the so-called“longest match”). A search for CO.18.0C.16 would match only the second,third, and fourth entries.

[0046] When multiple matches occur during a search, CAMs select the“best” entry by their physical addresses. Matches with lower addressesare selected over matches with higher addresses. For example, if asearch yields matches at CAM address 1 and 2, the match at address 1 isselected. In a typical layer 2 address filtering application, the orderof the entries in the CAM is unimportant because it is expected thatthere will be no more than one match result from any given search.

[0047] However, hierarchical address structures like IPv4, IPv4 CIDR,and IPv6 differ by having the possibility of having multiple matchesduring a search operation. The best match is the “longest match,” or theentry has the largest number of contiguous “cares” or 1s. Therefore, ifa CAM is used to store hierarchical addresses, sorting is necessary.There are two alternatives for this sorting: sorting when insertingentries, or sorting when reading matches. Fast hardware lookup for highbandwidth routing and switching places an emphasis on high-speedsearches. Choosing to sort when inserting entries is therefore a logicaldecision because it enables fast constant time address resolution.

[0048] Thus, as network communication speeds increase, there remains aneed to conduct hierarchical address translation at wirespeed, ratherthan relying on software techniques as is practiced in conventionaltranslation techniques, or on present CAM techniques. In particular,there remains a need for a method of sorting entries in the CAM toobtain the longest match in the shortest amount of time.

OBJECTS OF THE INVENTION

[0049] Accordingly, it is the general object of this invention toprovide an apparatus which improves upon and overcomes the disadvantagesof the prior art.

[0050] It is another object of this invention to provide fasterhierarchical address translation to most any hierarchical data.

[0051] It is another object of this invention to provide fasterhierarchical address translation by utilizing address resolution/searchthat is always completed in one CAM search cycle.

[0052] It is still another object of this invention to provide anapparatus and method having a sorting mechanism whose worst case costfor inserting new entries is proportional to the number of masks and isnot proportional to the number of entries.

[0053] It still yet another object of this invention to provide anapparatus and method whereby entries only need be sorted by mask levelswhich means that ordering inside mask levels is irrelevant.

[0054] It is even yet a further object of this invention to provide anapparatus and method using a sorting method whereby table updates can besuccessfully interrupted by searches as long as the current maintenanceatomic operation (e.g., an insert operation) is allowed to complete.

[0055] It is still yet a further object of this invention to provide anapparatus and method whereby each binary code pair, used to represent aternary value, are stored at n and n+32, thus making the binary toternary conversion easy to compute using a general purpose processor.

[0056] It is still yet a further object of this invention to provide anapparatus and method whereby the binary encoded ternary conversion isaccomplished inside the CAM itself to reduce the input/output bandwidth.

[0057] It is another object of this invention to provide an apparatusand method for faster hierarchical address translation for IP datagramrouters.

[0058] It is still another object of this invention to provide anapparatus and method for faster hierarchical address translation forlayer-3 switches.

[0059] It is still yet another object of this invention to provide anapparatus and method for faster hierarchical address translation in ATMswitches during connection setup for the translation of hierarchicalE.164 addresses.

[0060] It is still yet another object of this invention to provide anapparatus and method for faster hierarchical address translation fordata communication.

[0061] It is still yet another object of this invention to provide anapparatus and method for faster hierarchical address translation formultimedia communication.

[0062] It is still yet another object of this invention to provide anapparatus and method for faster hierarchical address translation forintegrated service communication.

[0063] It is even a further object of this invention to provide anapparatus and method for the encoding of ternary addresses in binaryCAMs.

[0064] It is yet another object of this invention to provide anapparatus and method for obtaining the longest-match ternary addressresolution in a single search cycle of a binary CAM.

[0065] It is still yet a further object of this invention to provide anapparatus and method for maintaining a sorted routing table for searchtechniques for binary CAMs.

[0066] It is still yet another object of this invention to provide anapparatus and method for maintaining a sorted routing table for ternaryCAM.

SUMMARY OF THE INVENTION

[0067] These and other objects of the instant invention are achieved byproviding a content addressable memory (CAM) of a communications system(e.g., data and telecommunication systems, network systems such asInternet Protocol, (IP), layer-3 switches and asynchronous transfer mode(ATM) used in E.164 addressing) utilizing ternary hierarchicaladdressing and associated address masks. The CAM (e.g., a ternary CAM ora binary CAM) comprises a plurality of address entries and associatedaddress masks that are arranged in the CAM by mask number, with addressentries having the highest mask number being located at address entrylocations at the top of the CAM and address entries having the lowestmask number being located at address entry locations at the bottom ofthe CAM (known as “partial ordering”). The mask number is defined as thenumber of contiguous ones in an associated address mask.

[0068] These and other objects of the instant invention are alsoachieved by providing an apparatus for storing a plurality of addressentries and associated address masks in a communication system (e.g.,data and telecommunication systems, network systems such as InternetProtocol, (IP), layer-3 switches and asynchronous transfer mode (ATM)used in E.164 addressing) utilizing ternary hierarchical addressing andassociated address masks. The apparatus comprises a binary CAM and abinary-encoded ternary (BET) conversion means coupled to the binary CAMwherein the BET conversion means converts each ternary value into acorresponding BET value to form the address entries. Furthermore, theplurality of address entries and associated address masks are arrangedin the binary CAM by mask number, with address entries having thehighest mask number being located at address entry locations at the topof the CAM and address entries having the lowest mask number beinglocated at address entry locations at the bottom of the CAM (known as“partial ordering”). The mask number is defined as the number ofcontiguous ones in an associated address mask.

[0069] These and other objects of the instant invention are alsoachieved by providing a method for accelerating the routing ofhierarchical addressing in a communication system which utilizes ternaryhierarchical addressing and associated address masks (e.g., data andtelecommunication systems, network systems such as Internet Protocol,(IP), layer-3 switches and asynchronous transfer mode (ATM) used inE.164 addressing). The method comprising the steps of: (a) obtainingcommunication system hierarchical addresses and associated masks to formaddress entries; and (b) storing the address entries in acontent-addressable memory (CAM) by mask number wherein the mask numberis defined as the number of contiguous ones in an associated addressmask and wherein address entries having the highest mask number arestored in address entry locations at the top of the CAM and addressentries having the lowest mask number are stored at address entrylocations at the bottom of the CAM (known as “partial ordering”).

[0070] These and other objects of the instant invention are alsoachieved by providing a method for maintaining a sorted CAM to enablelongest matches in a single search cycle when hierarchical addresses areadded to, or deleted from, the CAM in a communication system utilizinghierarchical addresses and associated address masks (e.g., data andtelecommunication systems, network systems such as Internet Protocol,(IP), layer-3 switches and asynchronous transfer mode (ATM) used inE.164 addressing). The method (known as “block-edge sorting”) comprisesthe steps of (a) segmenting the CAM into blocks wherein each blockcorresponds to a single hierarchical mask and wherein the blocks arearranged in the CAM such that the highest hierarchical masks are locatedat the lowest CAM addresses and the lowest hierarchical masks arelocated at the highest CAM addresses; (b) storing hierarchical addressesaccording to the block having a corresponding hierarchical mask; and (c)tracking (1) the first address of each of the blocks (floor); (2) thenext free address of each of the blocks (nxtfree); and (3) the size ofeach of the blocks.

DESCRIPTION OF THE DRAWINGS

[0071] Other objects and many of the attendant advantages of thisinvention will be readily appreciated as the same becomes betterunderstood by reference to the following detailed description whenconsidered in connection with the accompanying drawings wherein:

[0072]FIG. 1 is a prior art telephone number translation table;

[0073]FIG. 2 is the translation table of FIG. 1 re-arranged forconducting PATRICIA tree searching;

[0074]FIG. 3 is the translation table of FIG. 1 augmented by particularhierarchical levels, thereby permitting parallel searching;

[0075]FIG. 4 is a flow diagram for a prior art CAM search technique:Entries in Ternary CAMs with Hierarchical Level Field, Binary Search ofLevel Field;

[0076]FIG. 5 is a flow diagram for another prior art CAM searchtechnique: Full Sorted Order with Different Masks;

[0077]FIG. 6 is a flow diagram for another prior art CAM searchtechnique: Full Sorted Order;

[0078]FIG. 7 is a diagram of the structure of valid network masks;

[0079]FIG. 8 is a diagram of the structure of invalid network masks;

[0080]FIG. 9 is a diagram of addresses and masks from a CIDR routingtable;

[0081]FIG. 10 depicts a CAM using partial ordering in accordance withthe present invention;

[0082]FIG. 11 depicts a CAM that does not use partial ordering;

[0083]FIG. 12 is a flowchart for establishing partial ordering in a CAM;

[0084]FIG. 13 shows a portion of a communication system where a CAMusing partial ordering is used;

[0085]FIG. 14 depicts an exemplary communication system which uses CAMs;

[0086]FIG. 15 depicts a binary CAM with external binary-encoded ternary(BET) conversion means in a portion of a communication system using thepresent invention;

[0087]FIG. 16 depicts a binary CAM with internal binary-encoded ternary(BET) conversion means in a portion of a communication system using thepresent invention;

[0088]FIG. 17 depicts a ternary CAM in a portion of a communicationsystem using the present invention;

[0089]FIG. 18 depicts the contents of the binary CAM when binary-encodedternary (BET) conversion of the present application is applied;

[0090]FIG. 19 depicts the binary encoding of ternary values;

[0091]FIG. 20 depicts the CAM compare truth table with ternary values;

[0092]FIG. 21 depicts the CAM compare truth table; 10 FIG. 22 depictsthe storage of the IP address/IP mask of FIG. 18 in bits;

[0093]FIG. 23 depicts the relationship between the upper bits of FIG. 22(CO.18.0C.15) and the lower bits (3F.E7.F3.EA) of FIG. 22, the latter ofwhich is the one's complement of the upper bits;

[0094]FIG. 24 depicts a plurality of IP addresses/IP mask entries storedin the binary CAM in accordance with the present invention;

[0095]FIG. 25 depicts the compare results in accordance with the presentinvention;

[0096]FIG. 26 is a flowchart for the method of the present invention forstoring the binary-encoded ternary addresses in a binary CAM;

[0097]FIG. 27 is a flowchart of a binary CAM operation during a searchroutine;

[0098]FIG. 28 depicts insertion of a new hierarchical address entry intoa non-full block;

[0099]FIGS. 29a-29 c together depict the method for insertion of a newhierarchical address entry using one edge sort;

[0100]FIGS. 30a-30 c together depict the method for insertion of a newhierarchical address entry using two sorts;

[0101]FIGS. 31a-31 c together depict the method for insertion of a newhierarchical address entry recursive downward sorting;

[0102]FIGS. 32a-32 c together depict the method for upward insertion ofa new hierarchical address entry;

[0103]FIGS. 33a-33 c together depict the method for upward insertion ofa new hierarchical address entry using recursive upward sorting;

[0104]FIGS. 34a-34 b together depict the method for deleting any entry;and

[0105]FIG. 35 depicts an interleaving cycle for recursive sorting.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0106] Referring now in detail to the various figures of the drawingwherein like reference characters refer to like parts, there is shown at20 in FIG. 10, a CAM in which the address entries are arranged by masknumber (i.e., the number of contiguous ones in the mask), from thehighest mask number at the top of the CAM 20 to the lowest mask numberat the bottom, irregardless of the sequence of the addresses themselves.This arrangement, hereinafter known as “partial ordering (PO)”, isdepicted in that the addresses A, B, and C are not in alphabeticalorder, but are stored in the CAM in groups having the same mask numberand whereby these groups are stored in descending mask number order(which, by definition, is in increasing CAM address order). On the otherhand, FIG. 11 depicts a CAM that does not use PO. FIG. 12 depicts amethod 220 for optimally implementing a partially-ordered CAM 20,hereinafter known as “block-edge sorting (BES)”, and will be discussedin detail later. Suffice it to say for now that the “block-edge sorting”method is a specific application of PO.

[0107] Partial ordering incorporates significant advantages over thenumber of masks used in hierarchical address schemes. The primary searchadvantage is that the address resolution/search is always completed inone CAM search cycle. Furthermore, the primary sorting advantage to thisapproach is that the worst case cost for inserting new entries isproportional to the number of masks (N_(mask)), and is not proportionalto the number of entries.

[0108] The crucial realization of this algorithm is that entries onlyneed to be sorted by mask levels which means that ordering inside masklevels is irrelevant. Another advantage to the sorting method is thattable updates can be successfully interrupted by searches as long as thecurrent maintenance atomic operation (e.g., an insert) is allowed tocompletion.

[0109] At this point, it should be understood that the CAM 20 includesboth binary CAMs, as well as ternary CAMs, for storing the ternaryhierarchical addresses. As such, it is within the broadest scope of thepresent invention that PO and BES can be implemented using either binaryCAMs or ternary CAMs. Where a ternary CAM is used, the ternaryhierarchical address being stored (e.g., CO180000/16, the “C018” beinghexadecimal values and the “16” indicating the number of “cares”) wouldsimply be stored as is (i.e., C018XXXX). Where a binary CAM is used, theadditional steps of first converting the ternary hierarchical addressinto binary-encoded ternary (BET) and then storing the BET address in aunique manner (hereinafter, BETAS) in the binary CAM is discussed below.Thus, the following discussion is directed to the more-involvedsituation where a binary CAM is used, it being understood that use of aternary CAM would be a simpler case that would skip these additionalsteps.

[0110] As shown in FIG. 13, the CAM 20 using PO forms a portion (e.g.,an n-port router 22 that utilizes the CAM 20 for forwarding decisions)of a communications system (e.g., network 24, FIG. 14). The CAM 20interfaces with forwarding hardware 26 via a search data line 28 androuting decision line 30. The forwarding hardware 26 forms n networkinterfaces 32. It should be understood that the network 24 is exemplaryonly and that it is within the broadest scope of this invention toinclude the CAM 20 using PO in any type of communication system, e.g.,telecommunication system, data communication system, etc.

[0111] To place hierarchical entries in the CAM 20, it is necessary tosort their position in the CAM 20 so that the longest match is selectedfirst. Since CAMs select the best match by lowest CAM address value, theentries with the longest match mask are stored in the lowest CAMaddresses. If the following condition is met, a hierarchical addresssearch is guaranteed always to resolve to the longest match entry in oneCAM search cycle:

[0112] For all CAM 20 entries n: mask(n)≧mask(n+1)

[0113] As will be discussed in detail below, the PO of the presentinvention ensures that the CAM 20 entries are sorted properly so thatsearches always find the longest matching entry (i.e., the entry withthe most number of “1”s in its mask). By ensuring that the CAM 20entries are always ordered, the longest matching address is always foundwithin a single compare operation.

[0114] To implement the PO and BLS of the present invention using abinary CAM, for example, it is necessary to discuss how the BET(binary-encoded ternary) values are stored in the binary CAM 20 (FIGS.18-26). Next, a flowchart describing the CAM 20 operation during asearch is shown in FIG. 27. Then the BES method 220 (FIG. 12) isexplained using FIGS. (28-35).

[0115] BET Conversion/Storage in a Binary CAM (BETAS)

[0116] To facilitate IPv4 CIDR, a CAM 20 is split into separate groupsor blocks demarcated by IP mask values (FIG. 9). If a group of addressesthat share the same mask are to be stored, there must be some way ofencoding the “don't care” condition indicated by the address mask.Therefore, as discussed previously, two binary CAM bits are required toencode a single ternary (1, 0, X) entry. To binary encode the ternaryvalues (1, 0, X), 64 bits are required to store a 32-bit value.

[0117] The basic principle is that the binary value and its complementare stored if 1 or 0 is required, but when the “don't care” condition isneeded, 0 and 0 is stored. FIG. 19 shows how the three ternary valuesare encoded.

[0118] The actual BET conversion can be accomplished for the binary CAM20 either in external circuitry (FIG. 15, e.g., a separate IC 34A thatis located external of the CAM 20 or forms a portion 34B of theforwarding hardware 26) or in internal CAM 20 circuitry 36 (FIG. 16) toachieve the result of making a binary CAM appear as a ternary CAM to thesystem, whereby an N-bit binary CAM word acts a N/2-bit ternary CAMword. The advantage of using external circuitry 34A or 34B, is that itcan enhance system performance and increase maintainability.Alternatively, the advantage of using internal CAM circuitry 36 (e.g.,Music Semiconductors, Inc., assignee of the present invention, markets aCAM device with a built-in binary to ternary converter, part no.MUAC4K64, all of whose product literature is incorporated by referenceherein) is that doing so reduces the required input/output bandwidth bya factor of two. FIG. 17 depicts the situation where a ternary CAM isused and the ternary addresses are passed directly to the ternary CAM.

[0119] As an example of the BETAS of the present invention, the BETAS isused to store 32-bit ternary values as 64-bit binary encoded ternaryvalues in a 64-bit wide CAM. The high order bit of each 2-bit ternaryvalue is stored in the upper 32 bits of the CAM entry while the loworder bit is stored in the lower 32 bits of the CAM entry. For example,as shown in FIG. 22, to store C0.18.0C.15, bits 63:60 (C_(hex)) of theCAM entry would be 1100 and bits 31:28 would be 0011 (3_(hex)). This isequivalent to the ternary value 1100 as the binary encoded equivalent 1010 01 01. As can be seen most clearly from FIG. 23, the lower 32 bitsare simply the 1's complement of the upper 32 bits. This unique storagemechanism (BETAS) stores binary complementary values n bits apart, i.e.,the binary pair values at binary bit n and n+32, thereby making the BETconversion easy to compute using a general purpose processor.

[0120] To form the groups of addresses with the same IP masks, theindividual addresses have their masks added to them as they are insertedinto the CAM 20 memory array. To store an IP address and IP mask in a64-bit wide CAM 20 location, the bit-wise logical AND of the IP addressand IP mask are stored in the upper 32 bits while the bit-wise logicalAND of the mask and the address's 1's complement are stored in the lower32 bits. FIG. 18 shows how the IP address C0.18.0C.15 and the IP maskFF.FF.FF.FF would be stored in a CAM memory location according to theBETAS of the present application. FIG. 26 is a flowchart of how theaddress/mask are stored in the CAM 20 in accordance with the presentinvention.

[0121] Search of the CAM 20

[0122] The search method (FIG. 27) of the present invention alsoutilizes the BET scheme when searching the binary CAM 20 for a ternaryvalue. It is necessary incorporate a CAM mask register when the compareis performed. To search the CAM memory array for the ternary value 1, a“10” is loaded into both a Comparand register 38 and a Mask register 40(FIG. 20), which are both located in the CAM 20. The search would yieldthe results shown in FIG. 20. The ternary equivalent of each value isshown in parentheses after the binary-encoded value. The search resultedin the CAM entries 00 (X) and 10 (1) matching the Comparand register 38contents 10 (1). The contents of the Comparand register 38 iseffectively seen as X0 during the compare because the Mask register 40is also loaded with 10. This makes the first bit of the binary encodedvalue a “don't care” and will therefore match with either 1 or 0.Similarly a search for 01 (0) would produce a match with the CAM entries01 (0) and 00 (X). This effectively gives a match result when there is aternary X value, which is what is expected.

[0123] When the Mask register 40 is used to mask out bits during thecompare, it effectively allows ternary “don't cares” to be incorporatedduring a search. The Mask register 40 works in the opposite way from anIP mask. When the Mask register bit is set to 1, the result will alwaysbe a match condition. FIG. 21 shows the Truth Table of CAM comparesusing the Mask register 40.

[0124] There is enough information in each entry to determine theexplicit mask/address pair that generated it. For example, to search forthe entry C0.18.0C.15, a compare would be performed using C0.18.0C.15 asthe upper 32 bits and its 1's complement, 3F.E7.F3.EA, as the lower 32bits. The Mask register 40 also is loaded with the same value and isused when the compare takes place. The CAM Mask register 40 is used todetermine which bits take part in the search and which bits areeffectively ignored. As was seen in FIG. 20, the CAM mask works in theopposite way from an IP mask. This means that 1 corresponds to a “don'tcare” while a 0 corresponds to a “care” bit.

[0125] Each address is logical ANDed with the appropriate mask valuebefore being stored as binary encoded ternary. To perform a searchoperation using this searching method, the address being searched for iscopied to the upper 32 bits of both the Comparand register 38 and theMask register 40 and the 1's complement of the address is copied to thelower 32 bits. This again is loading the binary encoded ternaryequivalent. FIG. 24 shows how four 32-bit ternary values and their IPmasks would be encoded and stored in a 64-bit CAM.

[0126] Because of the ability to binary encode the ternary value X(“don't care”), the IP address and IP mask can be combined and stored as64 bits. These 64-bit values are stored in the binary CAM 20 memoryarray in IP mask order. That means, the IP mask values that have thehigher number of contiguous 1s are stored in the higher prioritylocations. How the CIDR entries are sorted into blocks, will bediscussed later.

[0127] If IP address C0.18.0C.15 were encoded in the normal manner andcompared with the four entries in FIG. 24, each entry would produce amatch result. If the entries were sorted properly, the highest prioritymatch would be entry number 1 (since that IP address has the highestnumber of contiguous 1s in its IP mask and was stored in the CAM in thehigher priority location), which would be the desired result. FIG. 25shows the results of the comparison between C0.18.0C.15 and entry number3, i.e., C0.18.0C.00. This shows how the combination of the binaryencoded ternary values and the use of the Mask register 40 work toproduce a match result.

[0128] An exemplary CAM 20 is the MUSIC Semiconductors WidePort LANCAM(all of whose product literature is incorporated by reference herein)which has a 32-bit I/O bus. This allows the 64-bit binary encodedternary values to be loaded into the Mask register 40 in two cycles. Thesearch procedure consists of the following:

[0129] 1. Two Short cycles—Load IP Address to bits [63:32] of Maskregister and load NOT (IP Address) to bits [31:0] OF Mask register.

[0130] 2. One Short cycle—Copy the Mask register to the Comparandregister.

[0131] 3. One Long cycle—Initiate a comparison with the CAM memory arraythrough the Mask register.

[0132] 4. One Medium cycle—Read out the CAM array address ofhighest-priority match. This address would be used as an index to accessassociated data stored in external RAM.

[0133] Using these five cycles, the search time required is as follows:

[0134] 50 ns speed grade CAM: 210 ns with a 15 ns clock, or 4.76 millionsearches per second.

[0135] 70 ns speed grade CAM: 280 ns with a 20 ns clock, or 3.57 millionsearches pre second.

[0136] Block-Edge Sorting Method

[0137] In FIG. 12, there is shown a flowchart for optimally implementinga partially-ordered CAM 20, which has been referred to as “block-edgesorting (BES)”. Thus, the goal of partial ordering is to maintain asorted CAM 20 to enable longest matches in one search cycle. Althoughapplicability of BES is being described for use with a binary CAM, BEScan also be used with ternary CAMs.

[0138] As stated previously, in order to obtain the longest match usingeither a binary CAM 20 or a ternary CAM, it is necessary to maintain theCAM 20 so that the ternary addresses with the larger mask numbers arestored in the higher priority addresses of the CAM 20. This conditioncan be summarized by the statement:

[0139] For any entry at address n, mask(n)≧mask (n+1)

[0140] As long as this condition is true for all addresses, the longestmatch is assured in one search cycle for lowest-address priority CAM's20. FIG. 10 shows a properly sorted CAM 20 that conforms to thecondition mask(n)≧mask(n+1). The letter in the notation “letter/number”can be interpreted as the address while the number corresponds to thehierarchical mask level. For instance, “A/32” matches “A/30” up to the30^(th) bit and is more of an exact match. A search for hierarchicaladdress “A” would match “A/32” first. In contrast, FIG. 11 shows CAMwith the condition mask(n)≧mask(n+1) violated. A search for “A” wouldget “A/30” instead of “A/32”, which is not the longest match and isincorrect.

[0141] The difficult task is to ensure this condition always exists asaddresses are added to and deleted from the CAM 20. The simple approachis to empty the CAM 20 every time it has to be updated and then reinsertevery entry. This can be a time-consuming process especially if therouting tables are not static and subject to dynamic changes. The timeto empty and refill the routing tables in the CAM 20 using this methodcould significantly decrease system performance and bandwidth.

[0142] A unique solution to this problem is to use a block-edge sortingalgorithm (FIG. 12) that enables real-time modification of the CAM 20routing table while reducing the time the CAM 20 cannot be searched toexceptionally low levels.

[0143] The block-edge sorting method takes a CAM 12 (or array of CAM'S)and segments the memory space in blocks. The block characteristics canbe represented in software or hardware as pointers and flags. Each blockcorresponds to one and only one hierarchical mask. For example, IPv4 hasat most 32 unique masks which would be represented by 32 CAM blocks.Hierarchical addresses are stored in their corresponding mask block. Theorder of the entries within each block is unimportant and is not kepttrack of because it is possible to get no more than one unique matchfrom each block. If more than one match does occur from a block, it canonly mean that there are multiple identical hierarchical address entriesin that block. The block-edge sorting method avoids the need to emptyand refill the CAM every time a new entry appears by reducing the worstcase to shuffling entries at the edges of each block. This method can beperformed either in an iterative or recursive manner.

[0144] The block characteristics consist of the:

[0145] Floor(f/): starting address index (known hereinafter as the“floor pointer”), which indicates the first address in the block;

[0146] Nxtfree (n/): the next free entry address index (knownhereinafter as the “next-free pointer”), which indicates the nextaddress to place an entry;

[0147] Blocksize: the block size of remaining entries; and

[0148] Backpressure flag: a flag or flags indicating the status of thefullness of the adjacent blocks in the hierarchy (known hereinafter asthe “back-pressure” flags), which indicates that this and all otherblocks “below” are filled.

[0149] The floor keeps track of the lowest address entry in thehierarchical block. The next-free pointer indicates the next destinationaddress for new address entries. The block size value in conjunctionwith the next-free pointer and the floor-pointer keeps track of whetheror not the block is full. Alternatively, a remaining entries counterrepresents the same information.

[0150] The first case for inserting a new hierarchical address entry iswhen the destination block has at least one free entry left. In thiscase, the new address is inserted at the location indicated by thenext-free pointer for the block. This case is shown in FIG. 28, wherethe new address is inserted and the next-free pointer is incremented toproperly indicate the next position for inserting entries.

[0151] If the sizes of each hierarchical block are carefully chosen soas to accurately represent the mask content of the routing tables beingstored, the majority if not all of the address inserts will be of thesimple default type described in FIG. 28. However, the block-edgesorting method expects this not to be the case and reacts accordingly tothe cases where a new address entry is being inserted into a block thatdoes not have any free entries left.

[0152] The next case, illustrated in FIGS. 29a-29 c, concerns when thedestination block is full. When the destination block is full, spacemust be allocated above or below the block to accommodate the new entry.In this example, of the block-sorting method and all followingillustrations, the block-edge sorting method prefers to steal space fromthe lowest hierarchical mask block adjacent to the one in question.However, the method applies in either initially stealing in the upwardsor downwards direction and loses no generality when illustrated in thedownwards direction. An optimal implementation might choose to sort inthe direction of the nearest free space, either above or below the fullblock in question. The downwards direction is selected only to beaesthetically consistent with the notion that higher mask prioritieshave precedence over lower mask priorities and the probability thatthere will be more entries with higher mask priorities.

[0153] In FIG. 29a, a new entry is shown with hierarchical mask level 32being inserted into block 32, which is represented by the floor-pointer“f/32” and the next-free pointer “n/32”, and the block size equal tothree, which can be inferred from the diagram by the block spacing.Block 32 is full, so the sorting algorithm looks at block 31, theadjacent block with lower mask priority. Block 31 is not full and theback-pressure flag is not set, therefore, there is a space in block 31to steal to accommodate block 32. FIG. 29b shows the floor entry A/31being moved to the next-free location in block 31. After A/31 is moved,so the new entry is moved to occupy the newly-freed location. Thepointers and block-sizes are adjusted to properly reflect the changes.In this case, block 32's size increases to 4 while block 31's sizedecreased to 3. Note that A/31 is now after B/31 which has no effectwhatsoever upon the proper sorting in the CAM 20 because the internalordering of blocks is irrelevant as long as the entries in the blockhave the same hierarchical mask numbers.

[0154]FIGS. 30a-30 c and FIGS. 31a-31 c show how the insertion methodextends to multiple blocks. In FIGS. 30a-30 c, the new entry is destinedfor block 32, which is full. There is at least one space somewherebetween that block and the highest memory address because noback-pressure flags are set. Due to this fact, the robbing will rippledownwards until it terminates successfully upon the first free entry.The moves are executed “backwards” from the terminating block to theinsertion of the new entry. This has to be done in order to prevententries from being overwritten before they are copied to their newlocation. In the case for FIGS. 30a-30 c, A/30 is moved to n/30, thenA/31 is moved to f/30, then new/32 is moved to f/31. FIGS. 31a-31 c showthat this sorting can scale to any number of blocks. The first freeentry below block 32 is in block 25. In this case, the terminating moveis the move of A/254 from f/25 to n/25. Block 32's steal carries all theway down to block 25, effectively stealing space from it as the onlychanges in block-sizes are in block 32 and block 25 where block 32increases to 4 and block 25 decreases to 3.

[0155] A special case to consider is when an entry is to be added to afull block and the blocks below are also full. When this occurs, entriescannot be swept further “downwards” to produce an empty location in therequired block. Instead, they must be pushed up if there is any freespace above. See FIGS. 32a-32 c.

[0156] A “Backpressure” flag, mentioned earlier, is set in the lastblock when there is no more space available. The meaning of the“backpressure flag” is this: if it is not set, there is at least onemore free entry somewhere between the current block and the highestphysical memory location. If it is set, then all blocks below thecurrent block are full. Blocks attempting to push downward check thisflag and, if it is set, are forced to try to push entries upward. Inthis case, recursion downward into the blocks would not work becausethere is no more free memory. Instead, recursion must go upwards. Thesame sorting routine is applied here with the difference being that thesorting goes in the opposite direction. FIGS. 33a-33 c show an exampleof recursive sorting upwards.

[0157] In FIG. 33a, a new entry is destined for the last block but it isfull, requiring the edge sorting to go upward instead of downward.Secondly, FIG. 33b shows the moves and inserts that will be done to freean entry space in the final block. As before, the Routing databasesorted in the CAM will always yield a correct search result due to theorder of the moves and inserts. Finally, FIG. 33c shows the blocks asrepresented by their readjusted pointers and block size values.

[0158] In order to delete entries from the CAM routing table and reusethe freed addresses, it is necessary to move the last entry in the blockto the address being deleted. FIGS. 34a-34 b shows the entry B/32 beingremoved form the routing table. First, E/32 is copied to B/32's address,overwriting and effectively deleting B/32. Then the entry E/32 at theoriginal location is deleted and the next-free pointer is decremented toproperly reflect the new spaces.

[0159] Depending upon how the routing table updates are performed, itmay be necessary to search for explicit IP address/mask combinations todetermine if an entry is already in the CAM 20. In this case, thelongest match is not what is being looked for. Therefore, the searchprocedure is slightly different from the one used to locate the longestmatch. When searching for the longest match, the Comparand register 38contents are duplicated in a Mask register 40 and the search isperformed with the relevant bits masked out.

[0160] When searching for explicit entries there is no need to use theMask register 40. The (ADDR & MASK), (!ADDR & MASK) representation ofthe IP address/mask pair is loaded into the Comparand register 38 and acompare is initiated. The address/mask pair is compared with the entriesin the CAM 20 memory array. This search will only yield a match if theCAM 20 entry exactly matches the entry in the Comparand register 38. TheLANCAM family has foreground and background register sets, which canmake this task easier.

[0161] The foreground registers should be set to do loading and searchesfor the longest matches as described earlier while the backgroundregisters should be set to perform explicit CAM searches that wouldperform compares without using a Mask register 40. It is then onlynecessary to switch between the two register sets as needed.

[0162] It is possible to interleave operations of the CAM 20 in order tokeep the table updated while continuing to perform high bandwidthsearches. For searches, the atomic operation is the five instructionload/load/copy/search/read index sequence. The insertion operation canbe broken up into different atomic operations that can be interleaved inbetween gaps in the atomic search operations. The following enumeratethe different atomic insert operations:

[0163] 1. Insert to address:

[0164] Two short cycles: load (ADDR & MASK) and (!ADDR & MASK)

[0165] One short cycle: insert to address

[0166] 2. Read out entry to be copied/moved

[0167]FIG. 35 shows how the four inserts (I) and three copies (C)required in the previous example on recursive sorting could be queuedand interleaved in between address searches (S). No operation isindicated by (N). The worst case number of cycles for this can becalculated assuming that the new entry is inserted to the first blockbut all blocks except the last are full. For k partitions there are:

[0168] k-1 CAM read cycles

[0169] k-CAM write cycles

[0170] k-RAM read/write cycles

[0171] An important point to note is that since k entries are moved, theoverhead of moving their associated data in RAM must also be considered.However, this worst case only happens once; with thoughtful initialblock allocation, inserting a new entry into the CAM will take one writecycle. A good precautionary measure to avoid long sorting operations isto adjust the block size and the spacing during idle periods to avoidshuffling during busy periods.

[0172] If the associated data entries stored in RAM are more than a fewbytes in length, a scheme using a second section of RAM to incorporatepointers might be considered The pointers would point to the associateddata entries of each CAM 20 entry, which would avoid moving large blocksof data. When the associated data entries are shuffled, it is a simplecase of rearranging the pointers. This would remove the need to move theassociated data around, which will reduce the associated datamaintenance time.

[0173] The methods described in present application are flexible enoughto be used with different styles of updating the routing tables andtherefore allows a system designer or software engineer the ability touse the most suitable method available. Using the algorithms describedin the present application in conjunction with dynamic routing tableupdates would be more efficient than reloading the routing table in theCAM and refilling it. This is because search operations could still beperformed during the updates.

[0174] Without further elaboration, the foregoing will so fullyillustrate our invention that others may, by applying current or futureknowledge, readily adopt the same for use under various conditions ofservice.

We claim:
 1. A content addressable memory (CAM) of a communicationssystem utilizing ternary hierarchical addressing and associated addressmasks, said CAM comprising a plurality of address entries and associatedaddress masks that are arranged in said CAM by mask number, with addressentries having the highest mask number being located at address entrylocations at the top of the CAM and address entries having the lowestmask number being located at address entry locations at the bottom ofthe CAM, said mask number being defined as the number of contiguous onesin an associated address mask.
 2. The CAM of claim 1 wherein said CAM isa ternary CAM.
 3. The CAM of claim 1 wherein said CAM is a binary CAM.4. The CAM of claim 3 further comprising binary-encoding ternary (BET)conversion means for converting each ternary value in said ternaryhierarchical address into a corresponding BET value to form said addressentries, said each ternary value being represented by first and secondbits of said corresponding BET value as follows: 0_(ternary)

01_(binary) 1_(ternary)

10_(binary) X_(ternary)

00_(binary), where X is defined as a “don't care” value, and whereinsaid first bit is stored in a first bit location in an upper portion ofsaid address entry location and wherein said second bit is stored in asecond bit location in a lower portion of said address entry location.5. The CAM of claim 4 wherein said first bit location and said secondbit location are separated by a predetermined number of bit locationsfrom each other.
 6. The CAM of claim 5 wherein said predetermined numberof bit locations is 32 based on 64-bit wide CAM entry size.
 7. The CAMof claim 1 wherein said communication system is a telecommunicationsystem.
 8. The CAM of claim 1 wherein said communication system is adata communication system.
 9. The CAM of claim 1 wherein saidcommunication system is a network system.
 10. The CAM of claim 9 whereinsaid network system is the Internet Protocol (IP) network.
 11. The CAMof claim 9 wherein said network comprises layer-3 switches.
 12. The CAMof claim 9 wherein said network comprises asynchronous transfer mode(ATM) switches using E.164 addressing.
 13. An apparatus for storing aplurality of address entries and associated address masks in acommunication system utilizing ternary hierarchical addressing andassociated address masks, said apparatus comprising: a binary CAM; abinary-encoded ternary (BET) conversion means coupled to said binary CAMwherein said BET conversion means converts each ternary value into acorresponding BET value to form said address entries; and wherein saidplurality of address entries and associated address masks are arrangedin said binary CAM by mask number, with address entries having thehighest mask number being located at address entry locations at the topof the CAM and address entries having the lowest mask number beinglocated at address entry locations at the bottom of the CAM, said masknumber being defined as the number of contiguous ones in an associatedaddress mask.
 14. The apparatus of claim 13 wherein said BET conversionmeans generates a BET value comprising a first bit and a second bit forevery ternary value of the ternary hierarchical address as follows:0_(ternary)

01_(binary) 1_(ternary)

10_(binary) X_(ternary)

00_(binary), where X is defined as a “don't care” value, and whereinsaid first bit is stored in a first bit location in an upper portion ofsaid CAM address entry location and wherein said second bit is stored ina second bit location in a lower portion of said CAM address entrylocation.
 15. The apparatus of claim 14 wherein said first bit locationand said second bit location are separated by a predetermined number ofbit locations from each other.
 16. The apparatus of claim 15 whereinsaid predetermined number of bit locations is 32 based on 64-bit wideCAM entry size.
 17. The apparatus of claim 16 wherein said communicationsystem is a telecommunication system.
 18. The apparatus of claim 16wherein said communication system is a data communication system. 19.The apparatus of claim 16 wherein said communication system is a networksystem.
 20. The apparatus of claim 19 wherein said network system is theInternet Protocol (IP) network.
 21. The apparatus of claim 19 whereinsaid network comprises layer-3 switches.
 22. The apparatus of claim 19wherein said network comprises asynchronous transfer mode (ATM) switchesusing E.164 addressing.
 23. A method for accelerating the routing ofhierarchical addressing in a communication system which utilizes ternaryhierarchical addressing and associated address masks, said methodcomprising the steps of: (a) obtaining communication system hierarchicaladdresses and associated masks to form address entries; and (b) storingsaid address entries in a content-addressable memory (CAM) by masknumber wherein said mask number is defined as the number of contiguousones in an associated address mask and wherein address entries havingthe highest mask number are stored in address entry locations at the topof the CAM and address entries having the lowest mask number beingstored at address entry locations at the bottom of the CAM.
 24. Themethod of claim 23 wherein said step of obtaining communication systemhierarchical addresses and associated masks comprises converting theternary hierarchical addresses and associated address masks intobinary-encoded ternary (BET) to form said address entries and whereinsaid CAM is a binary CAM.
 25. The method of claim 24 wherein eachternary hierarchical address and associated mask comprises a pluralityof ternary values and wherein said step of converting the ternaryhierarchical addresses and associated address masks into BET comprisesthe conversion of each of the ternary values into first and secondbinary-encoded ternary (BET) bits as follows: 0_(ternary)

01_(binary) 1_(ternary)

10_(binary) X_(ternary)

00_(binary), where X is defined as a “don't care” value.
 26. The methodof claim 25 wherein said step of storing said address entries in saidbinary CAM comprises storing said first bit in a first bit location inan upper location of said address entry location and wherein said secondbit is stored in a second bit location in a lower portion of saidaddress entry location.
 27. The method of claim 26 wherein said firstbit location and said second bit location are separated by apredetermined number of bit locations from each other.
 28. The method ofclaim 27 wherein said predetermined number of bit locations is 32 basedon 64-wide CAM entry size.
 29. The method of claim 24 wherein said stepof storing said address entries in said binary CAM comprises thefollowing steps: (a) logically ANDing the hierarchical address with itsassociated mask to form a first portion of said address entry; (b)logically ANDing the one's complement of the hierarchical address withits associated mask to form a second portion of said address entry; (c)selecting a CAM address entry location based on said mask number of saidassociated mask; and (d) storing said first portion in an upper portionof said selected address entry location and storing said second portionin a lower portion of said selected address entry location.
 30. Themethod of claim 29 comprising a searching method for searching the CAMupon receipt of a particular ternary hierarchical address and associatedmask input received from the communication system, said methodcomprising the steps of: (a) converting the particular ternaryhierarchical address input and associated mask into a BET input; (b)storing said BET input in the upper portion of a CAM comparand registerand storing the one's complement of said BET input in the lower portionof said CAM comparand register; (c) storing said BET input in the upperportion of a CAM mask register and storing the one's complement of saidBET input in the lower portion of said CAM comparand register; and (d)forming a one-to-one correspondence of each bit stored in said CAMcomparand register with a corresponding bit in said CAM address entrylocation and with a corresponding bit in said CAM mask register.
 31. Themethod of claim 30 further comprising the steps of: (a) declaring amatch between said CAM comparand register bit and its corresponding CAMaddress entry location bit: (1) whenever said corresponding CAM maskregister bit is a 1; or (2) whenever said corresponding CAM maskregister bit is a 0 and said corresponding CAM comparand register bit isidentical to its corresponding CAM address entry location bit; and (b)declaring no match between said CAM comparand register bit and itscorresponding CAM address entry location bit whenever said correspondingCAM mask register bit is a 0 and said corresponding CAM comparandregister bit is different from its corresponding CAM address entrylocation bit.
 32. The method of claim 23 wherein said communicationsystem is a telecommunication system.
 33. The method of claim 23 whereinsaid communication system is a data communication system.
 34. Theapparatus of claim 23 wherein said communication system is a networksystem.
 35. The apparatus of claim 34 wherein said network system is theInternet Protocol (IP) network.
 36. The apparatus of claim 34 whereinsaid network comprises layer-3 switches.
 37. The apparatus of claim 34wherein said network comprises asynchronous transfer mode (ATM) switchesusing E.164 addressing.
 38. A method for maintaining a sorted CAM toenable longest matches in a single search cycle when hierarchicaladdresses are added to, or deleted from, the CAM in a communicationsystem utilizing hierarchical addresses and associated address masks,said method comprising the steps of: (a) segmenting the CAM into blockswherein each block corresponds to a single hierarchical mask and whereinsaid blocks are arranged in the CAM such that the highest hierarchicalmasks are located at the lowest CAM addresses and the lowesthierarchical masks are located at the highest CAM addresses; (b) storinghierarchical addresses according to said block having a correspondinghierarchical mask; and (c) tracking (1) the first address of each ofsaid blocks (floor); (2) the next free address of each of said blocks(nxtfree); and (3) the size of each of said blocks.
 39. The method ofclaim 38 wherein if a block is full when an entry is trying to be madeinto said full block, said method further comprises the step of locatingthe closest block having at least one free memory space, therebydefining a non-full block.
 40. The method of claim 39 wherein saidnon-full block is located at higher CAM addresses, thereby definingblocks below said full block.
 41. The method of claim 40 furthercomprising the steps of: (a) moving the contents of said floor of saidnon-full block to said nxtfree of said non-full block; (b) for everyblock between said non-full block and said full block, in decreasing CAMaddress order, sequentially moving the contents of said floor of theupper block to said floor of the next lower block so that said floor ofsaid block directly below said full block is empty, thereby defining anempty location; (c) incrementing said floor of each of said blocks belowsaid full block to the next higher CAM address and incrementing saidnxtfree of each of said blocks below said full block to the next higherCAM address; and (d) moving the entry into said empty location.
 42. Themethod of claim 39 wherein said non-full block is located at lower CAMaddresses, thereby defining blocks above said full block.
 43. The methodof claim 42 further comprising the steps of: (a) moving the contents ofthe CAM address location that is directly above said nxtfree of theblock directly below said non-full block to the CAM address locationthat is directly above said floor of said block that is directly belowsaid non-full block; (b) for every block between said non-full block andsaid full block, in increasing CAM address order, sequentially movingthe contents of the CAM address location that is directly above saidnxtfree of the directly lower block and move said contents into the CAMaddress location directly above said floor of said lower block so thatCAM address location directly above said floor of said full block isempty, thereby defining an empty location; (c) decrementing said floorof each of said blocks above said full block to the next lower CAMaddress and decrementing said nxtfree of each of said blocks above saidfull block to the next lower CAM address; and (d) moving the entry intosaid empty location which is defined as a new floor for said full block.44. The method of claim 39 further comprising the step of deleting anentry from said CAM, said deleting step comprising: (a) moving a lastentry in a block into the CAM address location of said entry to bedeleted; and (b) decrementing said nxtfree of said block to CAM addresslocation of said last entry.
 45. The method of claim 43 furthercomprising the step of deleting an entry from said CAM, said deletingstep comprising: (a) moving a last entry in a block into the CAM addresslocation of said entry to be deleted; and (b) decrementing said nxtfreeof said block to CAM address location of said last entry.
 46. The methodof claim 38 further including the step of searching the CAM for a singlehierarchical network address entry having a mask, said single addressentry searching comprising the steps of: (a) logically ANDing thenetwork address and its respective mask to form a first CAM entryportion; (b) logically ANDing the one's complement of the networkaddress and its respective mask to form a second CAM entry portion; (c)loading said first and second CAM entry portions into a first registerof said CAM; and (d) comparing said first and second CAM entry portionswith said stored hierarchical addresses.
 47. The method of claim 38wherein said step of storing hierarchical addresses according to saidblock having a corresponding hierarchical mask comprises the insertionof each hierarchical address in said block in a non-sequential order.48. The method of claim 44 further comprising the step of interleavingsteps of said maintaining a sorted CAM between steps of a searchingmethod of said CAM in order to maintain said sorted CAM with minimalloss in performance whenever said communication system is operating atfull bandwidth.
 49. The method of claim 45 further comprising the stepof interleaving steps of said maintaining a sorted CAM between steps ofa searching method of said CAM in order to maintain said sorted CAM withminimal loss in performance whenever said communication system isoperating at full bandwidth.
 50. The method of claim 38 wherein saidcommunication system is a telecommunication system.
 51. The method ofclaim 38 wherein said communication system is a data communicationsystem.
 52. The method of claim 38 wherein said communication system isa network system.
 53. The method of claim 52 wherein said network systemis the Internet Protocol (IP) network.
 54. The method of claim 52wherein said network comprises layer-3 switches.
 55. The method of claim52 wherein said network comprises asynchronous transfer mode (ATM)switches using E.164 addressing.